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Top VHDL/Verilog Technology

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List Of The Top 100 VHDL/Verilog Technology

The listing of VHDL/Verilog Technology project is sorted out base on the user ratting, business category and VHDL/Verilog Technology project features. You can also find free VHDL/Verilog Technology projects for your business.

Logo Project Doodle Space
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Doodle Space

This is the source code for examples from my blog at http://wburris.com/...

This project was last updated September 24, 2022

Logo Project L2MI
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L2MI

L2MI - Little Modem Multiple Interface is a project that provide a firmware and hardware description of an educational Modem with multiple interfaces....

This project was last updated September 28, 2022

Logo Project dvi_enc
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dvi_enc

The dvi_enc is an example of implementation to Xilinx Spartan3A FPGA of the DVI encoder algorithm. It's written by Verilog HDL. And, the implementation supports XGA video mode....

This project was last updated September 24, 2022

Logo Project lfsr-counter-generator
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lfsr-counter-generator

A command-line application that generates Verilog or VHDL code for an LFSR counter of any value up to 63 bit wide. The code is written in C for Win32 platform...

This project was last updated September 28, 2022

Logo Project FPGA coprocessor floating point math lib
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FPGA coprocessor floating point math lib

libhdlfltp is a VHDL library of floating point operators, all of which are parametrized, synthesizable to FPGAs and cover a number of the core operators in math.h....

This project was last updated September 28, 2022

Logo Project EduCPU
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EduCPU

This is a simple CPU design, written in Verilog, intended for educational purposes. The objective is to provide a simulatable processor where the source code exposes concepts in CPU microarchitecture....

This project was last updated September 24, 2022

Logo Project Affordable BIOS Restoration Tool
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Affordable BIOS Restoration Tool

The Affordable BIOS Restoration Tool provides VHDL and C code to recover from failed BIOS upgrades using affordable CPLD's. EEPROM's and Flash chips can be restored with this flash programmer. Interfaces for DIP and tsop packages are being developed....

This project was last updated September 22, 2022

Logo Project accellera-vip-interop-library
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accellera-vip-interop-library

This library supports interoperability between components written for different verification methodologies such as VMM and OVM. This is maintained by the Accellera Verification Intellectual Property Technical Subcommittee....

This project was last updated September 22, 2022

Logo Project libVerilogVPI
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libVerilogVPI

SFENCE Extension Library (SEL) for access verilog function via PLI/VPI API to calls of standard SFENCE Function_Function objects....

This project was last updated September 28, 2022

Logo Project elphel-community
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elphel-community

This is a fork of the Elphel cameras firmware CVS, fully open to contributions from the elphel users and developers community Everyone can submit patches or obtain CVS access for this fork Stable changes will be ported to the main CVS upon approv...

This project was last updated September 24, 2022

Logo Project linux on fpga
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linux on fpga

The aim is to develop a foundation for a FPGA hardware platform able to run Linux kernel and software. It must be easy to add hardware accelerated ip-cores to the FPGA. Ethernet and TCP/IP is a corner stone of the hardware and software....

This project was last updated September 29, 2022

Logo Project linuxware
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linuxware

Linuxware is a hardware architechture that implements many linux system calls natively in hardware, to improve performance....

This project was last updated September 29, 2022

Logo Project EveSoc
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EveSoc

This project's goal is to provide a simple but extendable SOC (System On Chip) that can be loaded into an FPGA in order to quickly test custom coprocessors and evaluate their robustness against SCA (Side Channel Attacks) or others physical attacks....

This project was last updated September 25, 2022

Logo Project lpACLib
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lpACLib

The “lpACLib” library contains the VHDL description of accurate and approximate versions of several arithmetic modules (like adders and multiplier of different bit-widths) and accelerators. Moreover, it also provides the corresponding software behavioral models/implementations developed in C and MATLAB to enable qualit...

This project was last updated September 28, 2022

Logo Project FREE_VHD_Lib
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FREE_VHD_Lib

A free VHDL IPs for general purpose FPGA developpement. Need GRLIB to work properly, to setup see README. Automated GRLIB PatcherTarget Independent ...

This project was last updated September 28, 2022

Logo Project Elphel/Excelsior Eclipse/VDT/ExDT Plugin
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Elphel/Excelsior Eclipse/VDT/ExDT Plugin

Plugin Eclipse/VDT supports hardware development in VHDL/Verilog, allowing to easily integrate command-line controlled tools in Eclipse. Underlying Eclipse/ExDT plugin provides integration means that may be used for other languages and applications....

This project was last updated September 25, 2022

Logo Project FALCON Object Recognition System
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FALCON Object Recognition System

This is the award-winning FALCON I object recognition system! Capable of tracking up to 12 different objects simultaneously, and with over 6 times the raw resolution of the CMUCam, this is one of the most powerful vision systems in its class....

This project was last updated September 25, 2022

Logo Project ApproxAdderLib
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ApproxAdderLib

We provide MATLAB and Verilog Models of GeAr, and previously proposed adders (ACA-I, ETAII, ACA-II and GDA) at http://sourceforge.net/projects/approxadderlib/ GeAr is a low latency Generic Accuracy Configurable Adder that provides a higher number of potential configurations compared to state-of-the-art approximate adde...

This project was last updated September 22, 2022

Logo Project FAZIA DAQ
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FAZIA DAQ

The FAZIA project groups together more than 10 institutions in Nuclear Physics, which are working in the domain of heavy-ion induced reactions around and below the Fermi energy (10-100AMeV). The aim of the project is to build a 4Pi array for charged particles, with high granularity and good energy resolution, with A an...

This project was last updated September 25, 2022

Logo Project FPGA Build Tool
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FPGA Build Tool

Automatic build management for VHDL and Verilog projects. The automatic dependency resolver finds the exact subset of sources, and the correct order they must appear in required to build a project. A Makefile automates the actual build itself....

This project was last updated September 25, 2022

Logo Project Arduloko OS
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Arduloko OS

Sistema Operacional baseado no Ubuntu 11.04 (natty) 64bits destinado à profissionais e estudantes de eletrônica. O sistema foi gerado principalmente para trabalhos elaborados com o hardware arduino, mas foi evoluindo e hoje trabalha com vários outros equipamentos. A senha para login (Arduino ou root) é arduino. Para ba...

This project was last updated September 22, 2022

Logo Project ASDM-NoC
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ASDM-NoC

This project provide a reconfigurable asynchronous SDM router which can be configured into a basic wormhole router or an SDM router with multiple virtual circuits in every direction. Features: * 5-port router for mesh network (0 south, 1 west, 2 north, 3 east, 4 local) * The dimension order routing (XY routing) * Avai...

This project was last updated September 22, 2022

Logo Project MatlabSimulink2CPP
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MatlabSimulink2CPP

Video and files download for Visual trading idea to C++ or FPGA HFT Meetup File download sample: test model (Matlab 2014b with Visual Studio 2013 C++ project generated) Powerpoint MATLAB SIMULINK http://quantlabs.net/blog/2015/04/video-and-files-download-for-visual-trading-idea-to-c-or-fpga-hft-meetup/ Video and fi...

This project was last updated September 28, 2022

Logo Project AVRILOS
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AVRILOS

A simple Embedded System Framework that allows rapid development of applications build for AVR family. System is based on a super-loop architecture with check and skip (no-wait) flag event driver system. Supports: UART, SysTick Timer, ADC, SPI, EEPROM, PWM. Also supports: Xilinx FPGA configuration, FPGA SSI interface,...

This project was last updated September 22, 2022

Logo Project AXI4 BTC Miner
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AXI4 BTC Miner

Configurable FPGA bitcoin miner, from highest performance to the smallest footprint. Easy to implement thanks to its interface AXI4 lite. Generic or vendor specific implementation. Current performance are 300Mhash/s per core on a Xilinx Virtex-7....

This project was last updated September 22, 2022

Logo Project High Speed Vision System
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High Speed Vision System

This project aims to develop a colour-based vision processing system for use in RoboCup. We are using a CCD camera for input to an FPGA. The system locates coloured objects and outputs detected corners....

This project was last updated September 25, 2022

Logo Project FPGA Foosball
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FPGA Foosball

The foosball game is implemented in VHDL for use with the Altera DE2 FPGA board with the visual interface in a VGA monitor and input interface in a PS/2 keyboard. Works with Altera DE2 FPGA BoardAltera Quartus project files includedWritten entirely in VHDL ...

This project was last updated September 25, 2022

Logo Project Free tools and cores for FPGAs
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Free tools and cores for FPGAs

Tools for FPGA development and IP cores. This project provides tools, cores and documentation to develope FPGA applications. The project focuses on VHDL....

This project was last updated September 25, 2022

Logo Project FPGAmer
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FPGAmer

FPGAmer is a framework to develop embedded games. Our development platform is the Xilinx University Program Virtex-II-Pro but not limited to that. FPGAmer includes custom hardware components plus a custom software framework and some sample games....

This project was last updated September 25, 2022

Logo Project FPGA starterkit essentials
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FPGA starterkit essentials

Module 1: durchblicker: embedded Logicanalyzer with direct output on VGA-monitor storing fpga internal signals and display resulting waveform on vga-display2 cursor for measuring time delta and actual signal valuestrigger mode: auto, single, normal, falling, rising, external ...

This project was last updated September 25, 2022

Logo Project VHDL Test Processor
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VHDL Test Processor

Writing Testbenches for FPGA/ASIC design is always a very fastidious and boring task. This project helps any FPGA/ASIC designer by providing a full RTL test environment with C support....

This project was last updated September 25, 2022

Logo Project picode the VHDL ultimate pico-controller
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picode the VHDL ultimate pico-controller

Picode is the ultimate VHDL picode 16 to 32 bits controller. It is described in only one entity and is implementable in standard FPGAs. It has it own compiler. Picode is designed to take only one or two clock cycle duration per instruction....

This project was last updated September 29, 2022

Logo Project FPV OSD
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FPV OSD

This project implements an On Screen Display for FPV (First Person View) for RC planes. Sends telemetry data from GPS & sensors embebed with video information....

This project was last updated September 25, 2022

Logo Project freedaq
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freedaq

The purpose of this project is to design a completely open source hardware/software solution for experiment data acquisition and instrument control. The purpose is mostly educational, however the material provided will attempt to be of the highest quality....

This project was last updated September 25, 2022

Logo Project Mextram in Verilog-A
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This project was last updated September 29, 2022

Logo Project FPGA-Based Oscilloscope
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FPGA-Based Oscilloscope

Oscilloscope components, including 100MHz quad A/D, VHDL code for Xilinx FPGA, and driver for Octave or Matlab....

This project was last updated September 29, 2022

Logo Project FSMDesigner
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FSMDesigner

FSMDesigner is a C++ based implementation for a Finite State Machine (FSM) design tool with integrated Hardware Language (HDL) generation. FSMDesigner4 uses the Simple-Moore FSM model guaranteeing efficient fast complex control circuits. Create finite state machines for your hardware projectscomfortable and modern GU...

This project was last updated September 25, 2022

Logo Project PLP
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PLP

Powerful Verilog Preprocessor. PLP stands for Perl Pre-processor. Perl is used as "control language" that is embedded in the Verilog code (or any other code) to generate code on the fly. It is used commonly as a Verilog pre-processor but can be used with any target/output language (C, C++, Java, VHDL, plain text etc)...

This project was last updated September 29, 2022

Logo Project bel_fft
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bel_fft

bel_fft is a FFT co-processor that can calculate FFTs with arbitrary radix. It is a hardware implementation of the free software Kiss FFT ("Keep it simple, Stupid!"). The target was to allow a simple replacement of the software code with the hardware implementation. Therefore bel_fft comes with a software driver that i...

This project was last updated September 22, 2022

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Request Support from relates users

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Logo for App Guys Inc
5.0
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App Guys Inc

App Guys Inc Agency Profile Are we better? App-solutely! You want to change the world – we build the mobile applications, web apps and the websites to help you do it! You have an idea you want to bring to life and you can already imagine how it’s going to make people&

This Is The Top Of 66,613 Global Company

Logo for Segue Interactive Limited
5.0
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Segue Interactive Limited

Segue Interactive Limited is an ICT firm specializing in the development of creative, interactive, and user-friendly mobile and web apps. With a focus on delivering high-quality software with minimal risk, Segue Interactive has earned a reputation as one of the leading mobile dev

This Is The Top Of 66,613 Global Company

Logo for Mautilus
5.0
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Mautilus

Mautilus is a team of professionals with more than 10 years of experience in OTT multiscreen application development. We are also focused on developing applications for SmartHome, IoT, and VR & AR. At Mautilus, we take pride in our unique SmartTV SDK which allows building an

This Is The Top Of 66,613 Global Company

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Keep your customers in the loop—invite them as guest users or share a read-only view of your project's timeline.

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Keep track of VHDL/Verilog Technology project scope, schedule, milestones, dependencies, and most important metrics.

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Visualize and access real-time, high-level data for budgets, goals, schedules, resources, and more to make informed decisions more quickly and efficiently.

Workload view

Manage team resources, manage burnout, easily assign work, and adapt to changing priorities.

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Out-of-the-box reports and dashboards offer critical insights within the context of your work to ensure your teams are always up to date and set up for success.

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Cloodo is a flexible, innovative solution for people and organizations to achieve more with a complete developer platform to build, scale, and deliver any VHDL/Verilog Technology project.

Manage a private VHDL/Verilog Technology project

Just have a idea and you can create a VHDL/Verilog Technology project in private mode to keep developing it gradually or to share with your own team confidentially. When the project is ready you can publish it or made it become your portfolio or just keep it their personally.

Publish your VHDL/Verilog Technology project

Cloodo want to help any individual, team or company to show case their result of VHDL/Verilog Technology work as a public project. With Cloodo, any user can publishing your own VHDL/Verilog Technology project to make their profile shine, to invite more team member, calling for investors or get user feedback

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