Top Most Downloaded VHDL/Verilog Apps

Icarus Verilog is an open source Verilog compiler that supports the IEEE-1364 Verilog HDL including IEEE1364-2005 plus extensions....

The Red Pitaya is a commercial, affordable FPGA board with fast analog inputs and outputs. This makes it useful for quantum optics experiments, in particular as a digital feedback controller for analog systems. Based on the open source software provided by the board manufacturer, PyRPL (Python RedPitaya Lockbox) imple...

MiniLA logic analyzer software and hardware...

Firmware development/ improvement for the digital storage oscilloscope "Welec 2000a- series". https://github.com/alexvie/welecw2000a ...

VeriWell is a full Verilog simulator. It supports nearly all of the IEEE1364-1995 standard, as well as PLI 1.0. Yes, VeriWell *is* the same simulator that was sold by Wellspring Solutions in the mid-1990 and was included with the Thomas and Moorby book...

VHDL plugin based on http://sourceforge.net/projects/nppvhdlplugin/ This version is enhanced to include: - Insert Instantiation - Insert Signals - Create Test Bench Framework - Insert Component - Make comments Doxygen compliant - Create New Behavioral/Structural Entity Template - Create New Package File Template - In...

Verilog processor for Notepad++. Current features: - Instantiate a module - Insert registers/wires from a module - Generate a test bench template - Automatically inserts a default header for a test bench - Insert a clocked always block v1.2.0 now supports ANSI and non-ANSI module declarations. To use this plugin,...

GHDL is the leading open source VHDL simulator. *** Now on github.com/tgingold/ghdl *** We have binary distributions for Debian Linux, Mac OSX and Windows. On other systems, getting GHDL from here means downloading the current source package and building GHDL from source. Alternatively you can get the latest source ...

FSMDesigner is a C++ based implementation for a Finite State Machine (FSM) design tool with integrated Hardware Language (HDL) generation. FSMDesigner4 uses the Simple-Moore FSM model guaranteeing efficient fast complex control circuits. Create finite state machines for your hardware projectscomfortable and modern GU...

Tools for FPGA development and IP cores. This project provides tools, cores and documentation to develope FPGA applications. The project focuses on VHDL....

ADMS is a code generator that converts electrical compact device models specified in high-level description language into ready-to-compile c code for the API of spice simulators. Repository migrated to: https://github.com/Qucs/ADMS For checkout do: git clone https://github.com/Qucs/ADMS.git...

OpenSOC86 is an open implementation of the x86 architecture in Verilog. The current version only implements the 16-bit part (real mode). The processor is a pipelined architecture clocked at 100 MHz in a Cyclone II speed grade -6. Therefore it can be seen as similar to a 486 in real mode. Several peripherals are also i...

The “lpACLib” library contains the VHDL description of accurate and approximate versions of several arithmetic modules (like adders and multiplier of different bit-widths) and accelerators. Moreover, it also provides the corresponding software behavioral models/implementations developed in C and MATLAB to enable qualit...

Its a VHDL plugin for Notepad++ which is simular with the one which is available on emacs (Copy a selcted entity port and then paste it as instatiation , Signals or as Testbench )...

This is the award-winning FALCON I object recognition system! Capable of tracking up to 12 different objects simultaneously, and with over 6 times the raw resolution of the CMUCam, this is one of the most powerful vision systems in its class....

We provide MATLAB and Verilog Models of GeAr, and previously proposed adders (ACA-I, ETAII, ACA-II and GDA) at http://sourceforge.net/projects/approxadderlib/ GeAr is a low latency Generic Accuracy Configurable Adder that provides a higher number of potential configurations compared to state-of-the-art approximate adde...

A simple Embedded System Framework that allows rapid development of applications build for AVR family. System is based on a super-loop architecture with check and skip (no-wait) flag event driver system. Supports: UART, SysTick Timer, ADC, SPI, EEPROM, PWM. Also supports: Xilinx FPGA configuration, FPGA SSI interface,...

vrq is verilog parser that supports plugin tools to process verilog. Current plugins include tools to perform x-propagation and to auto build hiearchy....

A command-line application that generates Verilog or VHDL code for an LFSR counter of any value up to 63 bit wide. The code is written in C for Win32 platform...

Video and files download for Visual trading idea to C++ or FPGA HFT Meetup File download sample: test model (Matlab 2014b with Visual Studio 2013 C++ project generated) Powerpoint MATLAB SIMULINK http://quantlabs.net/blog/2015/04/video-and-files-download-for-visual-trading-idea-to-c-or-fpga-hft-meetup/ Video and fi...